NXP Semiconductors /MIMXRT1011 /IOMUXC /SW_MUX_CTL_PAD_GPIO_AD_02

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SW_MUX_CTL_PAD_GPIO_AD_02

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_AD_02 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: LPUART4_TXD of instance: LPUART4

1 (ALT1): Select mux mode: ALT1 mux port: LPSPI1_PCS1 of instance: LPSPI1

2 (ALT2): Select mux mode: ALT2 mux port: WDOG2_B of instance: WDOG2

3 (ALT3): Select mux mode: ALT3 mux port: LPI2C2_SCL of instance: LPI2C2

4 (ALT4): Select mux mode: ALT4 mux port: MQS_RIGHT of instance: MQS

5 (ALT5): Select mux mode: ALT5 mux port: GPIOMUX_IO16 of instance: GPIOMUX

7 (ALT7): Select mux mode: ALT7 mux port: ARM_CM7_TRACE_CLK of instance: cm7_mxrt

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_AD_02

Links

() ()